As is well known, it is necessary for a direct sequence receiver to synchronize a replica of a spreading code generated in the receiver with the spreading code in a received spread signal. The synchronization process falls into initial acquisition and tracking.
FIG. 1 is a block diagram showing a conventional DLL (Delay Locked Loop) used for the tracking. A spreading code replica is generated by a spreading code replica generator 1, and spreading codes whose phases are advanced and lagged by one chip with respect to the spreading code replica are fed to multipliers 3 and 4, respectively. The multipliers 3 and 4 take correlation between these spreading codes and the received spread signal. The correlation signals output from the multipliers 3 and 4 are passed through BPFs 5 and 6 which remove spurious high frequency components, and undergo square-law detection by square-law detectors 7 and 8. The outputs of the square-law detectors 7 and 8 are added in opposite phase by an adder 10 so that the phase error components are extracted between the received spreading code and the spreading code replica. The phase error components obtained are passed through a loop filter 11, and fed back to a voltage controlled clock generator 1. Thus, the generating phase of the spreading code replica is controlled so that its phase matches that of the received spreading code.
In this DLL, the signals after the correlation are passed through the square-law detectors to remove the residual frequency components of the carrier after the quadrature detection, or to remove the modulated components of the information data, which are contained in the signals after the correlation. Although this method has an advantage that the phase error can be easily extracted between the received spreading code and the spreading code replica, it has a disadvantage that noise and tracking jitter are increased because the noise components are also squared.